Electrostatic discharge (ESD) protection for high-voltage integrated circuits is challenging due to the requirement of high holding voltage to minimize the risk of ESD latchup. Silicon controlled rectifiers (SCR's) are attractive devices for ESD protection applications, for example because of their inherent bipolar conductivity modulation mechanism which can provide a deep snapback characteristic with a relatively small holding voltage, in the range of 1.0 to 2.0 V. This characteristic can reduce power dissipation in the SCR during an ESD event and result in a device which can be more robust when exposed to ESD than other devices such as diodes and grounded-gate NMOS (GGNMOS) devices.
A conventional twin-well SCR which can be used in low voltage ESD applications is depicted as a circuit schematic at FIG. 1, and as a cross section of one possible physical layout of the FIG. 1 circuit at FIG. 2. A top view of the FIG. 2 structure is depicted in FIG. 3.
FIG. 1 depicts a PNP parasitic bipolar junction transistor (BJT) 10, an NPN parasitic BJT 12, a first resistor R_pwell 14, and a second resistor R_nExt 16. The PNP device includes an emitter 18, a base 20, and a collector 22, and the NPN device has an emitter 24, a base 26, and a collector 28. The devices are electrically coupled with an anode 30, which can be coupled to a bond pad, and a cathode 32. The cross section of FIG. 2 depicts a cross section of one possible physical layout of the FIG. 1 circuit. FIG. 2 depicts anode 30, cathode 32, PNP emitter 18, base 20, and collector 22, NPN emitter 24, base 26, and collector 28. The PNP base 20 is provided by an N extension 33, which also provides R_nExt resistor 16. The NPN base 26 is provided by a P-well 34, which also provides R_pwell resistor 14. These structures can be formed within an N-type epitaxial layer 35, which in turn can be formed over a P-type silicon semiconductor substrate assembly 36. FIG. 2 further depicts isolation regions 38-46, which can be shallow trench isolation (STI) or LOCOS field isolation.
A blocking junction 48 of the N-Extension 33 and the P-Well 34 controls the SCR triggering. The doping of the N-Extension 33 and the P-Well 34 is designed to form a blocking junction 48 which yields a trigger voltage as high as 45 V for high-voltage ESD protection. Avalanche breakdown of this blocking junction 48 injects carriers into the N-Extension 33 and P-Well 34, thereby biasing the NPN 12 and PNP 10 transistors ON. Electrons added from the NPN emitter 24 and holes from the PNP emitter 18 reinforce the avalanche breakdown, creating a positive feedback. Once the gain of the system exceeds unity, the SCR will enter its ON state and the anode to cathode potential will drop to the holding voltage (VH).
The FIG. 2 structure can be implemented in the FIG. 3 top view of the FIG. 2 structure, demonstrating the use of strip technology. The topology depicted consists of a strip 18 of p-type dopant material which provides the P+ diffusion region for the emitter of the PNP device 10, and a strip 24 of n-type dopant material which provides the N+ diffusion region for the emitter of NPN device 12. The strips are uniformly doped with the appropriate dopant materials to the dopant concentrations sufficient for operation of the device. FIG. 2 further depicts a distance D1 which is the width of the PNP emitter 18 and NPN emitter 24, D2 which is the distance between the PNP emitter 18 and the NPN collector 28 and also the distance between the NPN emitter 24 and the PNP collector 22, D3 which is the width of the PNP collector 22 and also the width of the NPN collector 28, D4 which is the distance from the edge of the PNP collector 22 and the edge of the P Well 34 and also the distance from the edge of the NPN collector 28 and the edge of the N Extension 33, D5 which is the distance from the edge of the PNP emitter 18 and the blocking junction 48, and D6 which is the distance from the edge of the NPN emitter and the blocking junction 48. In addition to the features depicted in FIGS. 2 and 3, various other conventional features will be formed over and on the structures depicted in a completed semiconductor device.
When using SCR's for ESD protection of high-voltage integrated circuits, however, the small holding voltage VH becomes problematic, particularly for the case of a supply clamp connected between two supply rails with a voltage difference of more than 30 or 40 V. This is because the SCR is susceptible of being latched up unless the SCR's holding voltage is larger than the supply voltage difference. Specifically, in high voltage applications subsequent to an ESD event, an inability to shut off the latchup state can occur.
Various SCR structures aimed at increasing the holding voltage have been reported. For example, the article “High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps” (Vladislav A. Vashchenko, Ann Concannon, Marcel ter Beek, and Peter Hopper, IEEE Transactions on Device and Materials Reliability, vol. 4, pp. 273-280, June 2004) proposes a low-voltage trigger SCR (LVTSCR) with a high holding voltage based on reducing the parasitic BJT emitter area. However, the increase of the holding voltage was not sufficiently large for high-voltage IC ESD applications. Also, the article “ESD protection for high-voltage CMOS technologies” (Olivier Quittard, Zeljko Mrcarica, Fabrice Blanc, Guido Notermans, Theo Smedes, and Hans van Zwol, in Proc. EOS/ESD Symposium, pp. 77-86, 2006) proposes a structure which can be used to realize a high voltage supply clamp design by stacking several MOS transistors. However, this structure uses a large silicon area.
A device which provides an SCR for high voltage applications and which has a high holding voltage VH would be desirable.